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职责描述： 与设计架构师紧密合作，参与架构级别的讨论。 IP级设计规范和RTL编码 与综合和物理设计团队合作制定ASIC实施计划。 与验证工程师合作完成功能/性能测试计划。 任职要求： 2年或3年以上ASIC/SoC设计经验 较强的verilog开发实践经验 熟悉Perl、Makefile、 熟悉DSP, ARM, AXI优先考虑 熟悉内存控制器，有PCIE优先考虑。 较强的问题解决能力，团队合作和沟通能力 Participate in architecture level discussion by closely working with design architects. IP level design spec and RTL coding Coworking with synthesis and physical design team on the ASIC implementation plan. Coworking with verification engineers on the function/performance test plan. 任职要求：MS with 2 years or BS with 3 years’ experience in ASIC/SoC design Strong hands-on verilog development experience Familiar with scripting languages like Perl, Makefile, … Familiar with DSP, ARM, AXI is a plus Knowledge on memory controller, PCIE is a big plus. Strong problem solving, teamwork and communication skills